6522 PIA Register Map
The 6522 Programmable Interface Adapter has been mapped to the following addresses:
Port 'A' / 'B' Direction Registers [DDAC & DCNTRL]
The 'A' direction register [DDAC] controls the direction of data flow for
the 'A' data port [DAC].
The 'B' direction register [DCNTRL] controls the direction of data flow for
the 'B' data port [CNTRL].
Data flow direction is determined on a bit-by-bit basis. A '0' in a bit of
the data direction register causes the corresponding data port pin to act as an input.
A '1' causes the pin to act as an output.
Port 'A' Data ‑ DAC and PSG data [DAC]
When outputting data to the DAC, the data byte placed in the port 'A' data register
is in a two's complement format (bit 6 of the data byte is the high order bit with bit 0 being
the lowest. Bit 7 of the data byte is used for the sign). Therefore, the minimum hex value to
the DAC is $80, $00 is the centre point and $7F is the maximum.
When passing data with the programmable sound generator, the data direction will have
to be set according to the type of transfer.
Port 'B' Data ‑ Vectrex Hardware Control [CNTRL]
| Bit | Description |
| |
| 0 | Sample / Hold strobe
Normally high (binary 1). Setting low (binary 0) will strobe DAC value thru the multiplexer to selected sample / hold.
Minimum strobe time = Unknown
|
| 2 - 1 | Analog multiplexer select
Switch 'A'
| 00 | 'Y' axis sample / hold |
| 01 | Active ground |
| 10 | Intensity sample / hold |
| 11 | CPU sound |
Switch 'B'
| 00 | Controller #1: Right / Left joystick (POT0) |
| 01 | Controller #1: Up / Down joystick (POT1) |
| 10 | Controller #2: Right / Left joystick POT2) |
| 11 | Controller #2: Up / Down joystick (POT3) |
Settling time = Take a guess, everybody else did
|
| 3 | Sound generator, term 'BC1'
Register select for sound generator
|
| 4 | Sound generator, term 'BDIR'
Write control for sound generator
| BC1 | BDIR | Register |
| 0 | 0 | No select |
| 0 | 1 | Write to PSG data register |
| 1 | 0 | Read from PSG data register |
| 1 | 1 | Write address latch |
Settling time = Unknown
|
| 5 | Analog compare term (Input to 6522)
This signal results from the analog comparsion of the selected joystick pot versus the current
setting of the DAC. (If this term is high, the voltage of the DAC is greater than the voltage of POTx).
Settling time = Unknown ‑ no consensus
|
| |
| 6 | Available to cartridge connector |
| |
| 7 | Integrator ramp
Normally high (binary 1). While low (binary 0), the integration ramp will occur. The Vectrex
executive configures the 6522 so that this term is controlled by Timer #1 (low while counting, returns
to high when down-counted pass zero). |
Auxiliary Control Register [ACNTRL]
Peripheral Control Register [PCNTRL]
Port 'A' Handshake Controls (CA1 / 2)
CA1 is connected directly to button #4 of controller #2. It is on this pin that the light pen status
is brought into the Vectrex.
Driving CA2 low zeroes the integrators (Settling time is unknown). The integrators are normally
clamped (zeroed) when exiting one of the executive drawing routines. The integrators must be released prior to
ramping (this can be done by positioning the icon prior to drawing it).
PCNTRL
Bit 0 |
Description |
| |
| 0 | The CA1 interrupt flag (IFR1) will be set on a negative transition of the CA1 input pin. |
| |
| 1 | The CA1 interrupt flag (IFR1) will be set on a positive transition of the CA1 input pin.
The CA1 interrupt flag (IFR1) will be cleared on a read or write of the Port 'A' data register. |
| PCNTRL Bits |
| 3 | 2 |
1 | Description |
| |
| 0 | 0 | 0 |
Interrupt input mode ‑ Set CA2 interrupt flag (IFR0) on a negative transition of the CA2 input pin.
Clear the interrupt flag (IFR0) on a read or write of the Port 'A' data register. |
| |
| 0 | 0 | 1 |
Independent interrupt input mode ‑ Set CA2 interrupt flag (IFR0) on a negative transition of
the CA2 input pin. Reading or writing of the Port 'A' data register does not affect the status of
the interrupt flag (IFR0). |
| |
| 0 | 1 | 0 |
Interrupt input mode ‑ Set CA2 interrupt flag (IFR0) on a positive transition of the CA2 input pin.
Clear the interrupt flag (IFR0) on a read or write of the Port 'A' data register. |
| |
| 0 | 1 | 1 |
Independent interrupt input mode ‑ Set CA2 interrupt flag (IFR0) on a positive transition of
the CA2 input pin. Reading or writing of the Port 'A' data register does not affect the status
of the interrupt flag (IFR0). |
| |
| 1 | 0 | 0 |
Handshake output mode ‑ Set CA2 output pin low on a read or write of the Port 'A' data register.
Reset CA2 pin to high with an active transition of the CA1 input pin. |
| |
| 1 | 0 | 1 |
Pulse output mode ‑ CA2 goes low for one cycle following a read or write of the Port 'A' data
register. |
| |
| 1 | 1 | 0 |
Manual output mode ‑ The CA2 output is held low in this mode. |
| |
| 1 | 1 | 1 |
Manual output mode ‑ The CA2 output is held high in this mode. |
Port 'B' Handshake Controls (CB1 / 2)
The term CB1 is not currently connected.
Driving CB2 low, blanks the video output (over-riding the shift register's control over video on ‑ off).
The executive does not use this control, but does set it high during initialization.
PCNTRL
Bit 4 |
Description |
| |
| 0 |
The CB1 interrupt flag (IFR4) will be set on a negative transition of the CB1 input pin. |
| |
| 1 |
The CB1 interrupt flag (IFR4) will be set on a positive transition of the CB1 input pin.
The CB1 interrupt flag (IFR4) will be cleared on a read or write of the Port 'B' data register. |
| PCNTRL Bits |
| 7 | 6 | 5 |
Description |
| |
| 0 | 0 | 0 |
Interrupt input mode ‑ Set CB2 interrupt flag (IFR3) on a negative transition of the CB2 input pin.
Clear the interrupt flag (IFR3) on a read or write of the Port 'B' data register. |
| |
| 0 | 0 | 1 |
Independent interrupt input mode ‑ Set CB2 interrupt flag (IFR3) on a negative transition of
the CB2 input pin. Reading or writing of the Port 'B' data register does not affect the status of
the interrupt flag (IFR3). |
| |
| 0 | 1 | 0 |
Interrupt input mode ‑ Set CB2 interrupt flag (IFR3) on a positive transition of the CB2 input pin.
Clear the interrupt flag (IFR3) on a read or write of the Port 'B' data register. |
| |
| 0 | 1 | 1 |
Independent interrupt input mode ‑ Set CB2 interrupt flag (IFR3) on a positive transition
of the CB2 input pin. Reading or writing of the Port 'B' data register does not affect the
status of the interrupt flag (IFR3). |
| |
| 1 | 0 | 0 |
Handshake output mode ‑ Set CB2 output pin low on a read or write of the Port 'B' data register.
Reset CB2 pin to high with an active transition of the CB1 input pin. |
| |
| 1 | 0 | 1 |
Pulse output mode ‑ CB2 goes low for one cycle following a read or write of the
Port 'B' data register. |
| |
| 1 | 1 | 0 |
Manual output mode ‑ The CB2 output is held low in this mode. |
| |
| 1 | 1 | 1 |
Manual output mode ‑ The CB2 output is held high in this mode. |
Timer #1
| Addr |
Label | Description |
| |
| $D004 | T1LOLC |
Write into low order latch
Read from low-order counter and reset interrupt |
| |
| $D005 | T1HOC |
Write into high-order latch, transfer latches to counter and reset interrupt
Read from high-order counter |
| |
| $D006 | T1LOL |
Write into low-order latch
Read from low-order latch |
| |
| $D007 | T1HOL |
Write into high-order latch and reset timer #1 interrupt
Read from high-order latch |
| ACNTRL Bits |
| 7 | 6 |
Description |
| |
| 0 | 0 |
Generate a single time-out interrupt each time timer #1 is loaded. Output pin PB7 is disabled. |
| |
| 0 | 1 |
Generate continuous interrupts. Output pin PB7 is disabled. |
| |
| 1 | 0 |
Generate a single interrupt and an output pulse on pin PB7 for timer #1 load operation. |
| |
| 1 | 1 |
Generate continuous interrupts and a square wave output on pin PB7. |
One-shot Mode
The one-shot mode allows generation of a single interrupt each time a load operation occurs.
In addition to generating a single interrupt, Timer #1 can be programmed to produce a single negative pulse
on the PB7 peripheral pin. With the output enabled (ACNTRL7 = 1), a write to location $D005 [T1HOC] will
cause PB7 to go low. PB7 will return high when Timer #1 counts down to zero. For PB7 to act as the output
of Timer #1, both the direction register for Port 'B' (bit 7) and the auxiliary control register (bit 7)
must be set (e.g. - DCNTRL7 = 1 .and. ACNTRL7 = 1).
It is necessary to assure that the low order latch contains the proper data before initiating
the count-down by writing to location $D005 [T1HOC]. When starting the down-count, the interrupt flag is cleared,
the contents of the low-order latch will be transferred into the low-order counter and the timer will begin to
decrement at the system clock rate. If the PB7 output is enabled, this signal will go low on the phase two
following the write operation.
When the counter reaches zero, the timer #1 interrupt flag will be set, the IRQ pin will go low
and the signal on PB7 will go high. The counter will still continue to decrement, this will allow the time
since the interrupt to be determined (note: the timer #1 interrupt will not be set again unless it has
previously cleared).
Free-running Mode
The most important advantages associated with the latches are the ability to produce a
continuous series of evenly spaced interrupts and the ability to produce a square wave on PB7 whose
frequency is not affected by variations in the processor interrupt response time.
In the free-running mode (ACNTRL6 = 1), the interrupt flag is set and the signal on PB7 is
inverted each time the counter reaches zero. However, instead of continuing to decrement from zero after
a time-out, the timer automatically transfers the contents of the latch into the counter and
continues to decrement from there.
Timer #2
| Addr |
Label | Description |
| |
| $D008 | T2LOLC | Write into low-order latch
Read from low-order counter and reset interrupt |
| |
| $D009 | T2HOC |
Write into high-order latch, transfer latches to counter and reset interrupt
Read from high-order counter |
ACNTRL
Bit 5 |
Description |
| |
| 0 | Interval timer mode ‑ As an interval timer, Timer #2 operates in
one-shot mode similiar to Timer #1. In this mode, Timer #2 provides a single interrupt for each T2HOC operation.
After timing out, the counter will continue to decrement. However, setting of the interrupt flag will be disabled
after initial time-out so that it will not be set by the counter continuing to decrement through zero. The
processor must rewrite T2HOC to enable setting of the interrupt flag. The interrupt flag is cleared by
reading T2LOLC or by writing T2HOC. |
| |
| 1 | Pulse counting mode ‑ This is accomplished by first loading a
number into T2LOLC. Writing into T2HOC clears the interrupt flag and allows the counter to decrement each
time a pulse is applied to PB6. The interrupt flag will be set when Timer #2 reaches zero. The timer will continue
to down-count with each pulse on PB6. However, it is necessary to rewrite T2HOC to allow the interrupt flag
to set on subsequent down-counting operations. The pulse must be low on the leading edge of the
phase 2 clock. |
Interval Timer Mode
In interval timer mode, Timer #2 operates in the 'one-shot' mode similar to timer #1. Timer #2 issues
an interrupt for each timer load operation. After timing out, the counter will continue to decrement.
Pulse-counting Mode
In the pulse counting mode, Timer #2 serves primarily to count a predetermined number of negative
transitions on PB6. Writing into $D009 [T2HOC] clears the interrupt flag and allows the counter to decrement for
each negative transition applied to PB6. The interrupt flag will be set when Timer #2 reaches zero.
At this time the counter will continue to decrement with each negative transition on PB6.
The pulse must be low on the leading edge of phase two.
Shift Register [SHIFT]
The shift register performs serial data transfers into and out of the CB2 pin under control of an
internal modulo-8 counter. Shift pulses can be applied to the CB1 pin from an external source or, with the proper
mode selection, shift pulses generated internally will appear on the CB1 pin for controlling shifting in
external devices.
The control bits which allow control of the various shift register operating modes are located in
the the Auxiliary control register [ACNTRL]:
| ACNTRL Bits |
| 4 | 3 | 2 |
Description |
| |
| 0 | 0 | 0 |
Shift register disabled |
| |
| 0 | 0 | 1 |
Shift-in under control of Timer #2 |
| |
| 0 | 1 | 0 |
Shift-in at system clock rate |
| |
| 0 | 1 | 1 |
Shift-in under control of external pulses |
| |
| 1 | 0 | 0 |
Shift-out under control of Timer #2 |
| |
| 1 | 0 | 1 |
Shift-out under control of Timer #2 |
| |
| 1 | 1 | 0 |
Shift-out at system clock rate |
| |
| 1 | 1 | 1 |
Shift-out under control of external pulses |
The data shifted-out of the shift register appears from bit 7 (note: at the same time,
bit 7 is shifted-in at bit 0).
The first two shift-out modes differ in that the second mode (1 0 1) places the shift
pulses on the CB1 pin.
The shift-in modes are not used with the standard Vectrex hardware and are described only
for reference.
Interrupt Enable Register [IENABL]
Enabling flags ‑ When writing to the Interrupt enable register ($D00E) and bit 7 is set,
then each 1 in bits 6 through 0 sets the corresponding bit in the Interrupt enable register.
Disabling flags ‑ When writing to the Interrupt enable register ($D00E) and bit 7 is cleared,
then each 1 in bits 6 through 0 sets the corresponding bit in the Interrupt enable register.
| Bit | Description |
| |
| 0 | Enable / disable 'CA2' flag |
| |
| 1 | Enable / disable 'CA1' flag |
| |
| 2 | Enable / disable Shift register done flag |
| |
| 3 | Enable / disable 'CB2' flag |
| |
| 4 | Enable / disable 'CB1' flag |
| |
| 5 | Enable / disable Timer #2 flag |
| |
| 6 | Enable / disable Timer #1 flag |
| |
| 7 | Set / clear control |
Interrupt Flag Register [IFLAG]
| Bit | Description |
| |
| 0 | Set by an active transition of 'CA2' signal
Cleared by the reading or writing of the Port 'A' data register (register address $D001).
Reading or writing the Port 'A' data at register address $D00F does not affect the setting
of this bit. |
| |
| 1 | Set by an active transition of 'CA1' signal
Cleared by the reading or writing of the Port 'A' data register (register address $D001).
Reading or writing the Port 'A' data at register address $D00F does not affect the setting
of this bit. |
| |
| 2 | Shift register done
Cleared by the reading or writing of the shift register (register address $D00A). |
| |
| 3 | Set by an active transition of 'CB2' signal
Cleared by the reading or writing of the Port 'B' data register (register address $D000). |
| |
| 4 | Set by an active transition of 'CB1' signal
Cleared by the reading or writing of the Port 'B' data register (register address $D000). |
| |
| 5 | Timer #2 has down-counted to zero
Cleared by reading Timer #2's low-order counter (register address $D008) or writing Timer #2's high-order
counter (register address $D009). |
| |
| 6 | Timer #1 has down-counted to zero
Cleared by reading Timer #1's low-order counter (register address $D004) or writing Timer #1's high-order
counter (register address $D005). |
| |
| 7 | Logic expression of (IFR6 .and. IER6) .or. (IFR5 .and. IER5) .or.
(IFR4 .and. IER4) .or. (IFR3. and. IER3) .or. (IFR2 .and. IER2) .or. (IFR1 .and. IER1) .or.
(IFR0 .and. IER0) |