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Vectrex Programmer's Guide

Programmable Sound Generator (PSG)


Register Access Map



Reg   Description
 
$00   Channel A: Fine tone period
 
$01   Channel A: Course tone period
 
$02   Channel B: Fine tone period
 
$03   Channel B: Course tone period
 
$04   Channel C: Fine tone period
 
$05   Channel C: Course tone period
 
$06   Noise period
 
$07   Tone / Noise enables
 
$08   Channel A: Amplitude
 
$09   Channel B: Amplitude
 
$0A   Channel C: Amplitude
 
$0B   Fine envelope period
 
$0C   Course envelope period
 
$0D   Envelope shape / cycle
 
$0E   I/O Port

Tone / Noise Enables

The mixers combine the noise and tone frequencies for each of the three channels. The determination of combining neither / either or both noise and tone on each channel is made by state of the bits below:

Tone Enables:

2 1 0   Description
 
x x 0   Enable Channel A tone
x x 1   Disable Channel A tone
 
x 0 x   Enable Channel B tone
x 1 x   Disable Channel B tone
 
0 x x   Enable Channel C tone
1 x x   Disable Channel C tone

Noise Enables:

5 4 3   Description
 
x x 0   Enable Channel A noise
x x 1   Disable Channel A noise
 
x 0 x   Enable Channel B noise
x 1 x   Disable Channel B noise
 
0 x x   Enable Channel C noise
1 x x   Disable Channel C noise

Note that disabling noise and tone does not turn-off a channel. Turning a channel off can only be accomplished by writing all zeroes into the corresponding amplitude control register.

The direction (input or output) of the two general purpose I/O ports is determined by the state of the bits below:

7 6   Description
 
x 0   I/O Port A: Input
x 1   I/O Port A: Output
 
0 x   I/O Port B: Input
1 x   I/O Port B: Output

Course / Fine Tone Period

The frequency of each square wave generated by the three Tone generators is obtained in the PSG by first counting down the input clock by 16, then by further counting down the result by the programmed 12-bit tone period value. The 12-bit tone period is formed by the lower 4-bits of the course tone period (the upper 4-bits of the course tone period are not used) and the full byte of the fine tone period.

Note that the 12-bit value programmed in the combined course and fine tone registers is a 'period' value - the higher the value in the registers, the lower the resultant tone frequency. (The lowest period value is $001).

Channel Amplitude

The amplitudes of the signals generated by the three D/A converters (one for each channel) is determined by the contents of the lower 5 bits (B4 - B0) of registers $08, $09 and $0A.

The amplitude mode (bit 4) selects either fixed level amplitude (M = 0) or variable level amplitude (M = 1). It follows then that bit 3 thru 0 are only active when M = 0. When fixed level amplitude is selected, it is 'fixed' only in the sense that the amplitude level is under the direct control of the system processor. Varying the amplitude when in this 'fixed' amplitude mode requires in each instance the direct intervention of the system processor via an address latch / write data sequence to modify the amplitude setting.

When M = 1, the amplitude of each channel is determined by the envelope pattern as defined by the envelope generator's 4-bit output. The amplitude mode (bit 'M') should be thought of as an envelope enable bit.

Noise Period

The frequency of the noise source is obtained in the PSG by first counting down the input clock by 16, then by further counting down the result by the programmed 5-bit noise period value. This 5-bit value consists of the lower 5 bits of register $06.

Note that the 5-bit value in register $06 is a period value - the higher the value in the register, the lower the resultant noise frequency (the lowest period is $01).

Envelope Period

The frequency of the envelope is obtained in the PSG by first counting down the input clock by 256, then by further counting down the result by the programmed 16-bit envelope period value. This 16-bit value is formed by the course and fine envelope period registers. Note that the 16- bit value formed by the course and fine envelope period registers is a period value - the higher the value in the registers, the lower the resultant envelope frequency (the lowest period is $0001).

Envelope Shape / Cycle

The particular shape and cycle pattern of any desired envelope is accomplished by the count pattern of the 4-bit envelope pattern (up / down) and by defining a single-cycle or repeat-cycle pattern. The envelope shape / cycle is controlled by the bits below:


Bit   Description
 
0   Hold:

1 - Limits the envelope to one cycle, holding the last count of the envelope counter.

 
1   Alternate:

1 - The envelope counter reverses count direction (up / down) after each cycle.

 
2   Attack:

0 - The envelope counter will count down (decay).

1 - The envelope counter will count up (attack).

 
3   Continue:

0 - The envelope counter will reset after one cycle and hold.

1 - The cycle pattern is defined by the hold bit (bit 0).

Note that when both the hold and alternate bits are set to '1', the envelope counter is reset to its initial count after holding.



 
 
 
 
 
 

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This page was last modified: 12 Jan 2017
By John Hall